SWREQ=HWR_CONNECTED, SIF=AHB_IF0, WRIP=DONE, INITD=IN_PROGRESS, CSIZE=CHK_1, DWIDTH=BYTE, DAM=FIXED_AM, RDIP=DONE, DIF=AHB_IF0, SAM=FIXED_AM, DSYNC=PER2MEM, MEMSET=NORMAL_MODE, TYPE=MEM_TRAN, MBSIZE=SINGLE
Channel Configuration Register (chid = 0)
| TYPE | Channel x Transfer Type 0 (MEM_TRAN): Self triggered mode (Memory to Memory Transfer). 1 (PER_TRAN): Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). |
| MBSIZE | Channel x Memory Burst Size 0 (SINGLE): The memory burst size is set to one. 1 (FOUR): The memory burst size is set to four. 2 (EIGHT): The memory burst size is set to eight. 3 (SIXTEEN): The memory burst size is set to sixteen. |
| DSYNC | Channel x Synchronization 0 (PER2MEM): Peripheral to Memory transfer. 1 (MEM2PER): Memory to Peripheral transfer. |
| SWREQ | Channel x Software Request Trigger 0 (HWR_CONNECTED): Hardware request line is connected to the peripheral request line. 1 (SWR_CONNECTED): Software request is connected to the peripheral request line. |
| MEMSET | Channel x Fill Block of memory 0 (NORMAL_MODE): Memset is not activated. 1 (HW_MODE): Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. |
| CSIZE | Channel x Chunk Size 0 (CHK_1): 1 data transferred 1 (CHK_2): 2 data transferred 2 (CHK_4): 4 data transferred 3 (CHK_8): 8 data transferred 4 (CHK_16): 16 data transferred |
| DWIDTH | Channel x Data Width 0 (BYTE): The data size is set to 8 bits 1 (HALFWORD): The data size is set to 16 bits 2 (WORD): The data size is set to 32 bits |
| SIF | Channel x Source Interface Identifier 0 (AHB_IF0): The data is read through the system bus interface 0. 1 (AHB_IF1): The data is read through the system bus interface 1. |
| DIF | Channel x Destination Interface Identifier 0 (AHB_IF0): The data is written through the system bus interface 0. 1 (AHB_IF1): The data is written though the system bus interface 1. |
| SAM | Channel x Source Addressing Mode 0 (FIXED_AM): The address remains unchanged. 1 (INCREMENTED_AM): The addressing mode is incremented (the increment size is set to the data size). 2 (UBS_AM): The microblock stride is added at the microblock boundary. 3 (UBS_DS_AM): The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. |
| DAM | Channel x Destination Addressing Mode 0 (FIXED_AM): The address remains unchanged. 1 (INCREMENTED_AM): The addressing mode is incremented (the increment size is set to the data size). 2 (UBS_AM): The microblock stride is added at the microblock boundary. 3 (UBS_DS_AM): The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. |
| INITD | Channel Initialization Terminated (this bit is read-only) 0 (IN_PROGRESS): Channel initialization is in progress. 1 (TERMINATED): Channel initialization is completed. |
| RDIP | Read in Progress (this bit is read-only) 0 (DONE): No Active read transaction on the bus. 1 (IN_PROGRESS): A read transaction is in progress. |
| WRIP | Write in Progress (this bit is read-only) 0 (DONE): No Active write transaction on the bus. 1 (IN_PROGRESS): A Write transaction is in progress. |
| PERID | Channel x Peripheral Hardware Request Line Identifier |